1. Field of the Invention
This invention relates to a CMOS self-biased comparator, and more particularly to a pseudo-ECL receiver and a binary-to-multi-level-transition (MLT-3) decoder each using the CMOS self-biased comparator.
2. Description of the Related Art
High-speed communications networks such as Fast (100 Mbps) Ethernet and asynchronous-transfer-mode (ATM) networks use differential signals for transmitting data. The speed of these differential signals is increased when they transition over a reduced voltage range, since output capacitances are charged and discharged over a smaller voltage range, requiring less current.
Small-signal differential drivers and differential amplifiers are needed for these network applications. In the past, bipolar NPN transistors arranged as emitter-coupled-logic (ECL) gates were used. However, complementary metal-oxide-semiconductor (CMOS) is a less expensive technology than bipolar. Bipolar NPN transistors have been integrated into CMOS processes resulting in a technology known as BiCMOS. Although BiCMOS is fast, it is also more expensive than standard CMOS.
Small-signal techniques have been used for BiCMOS and CMOS using pseudo-ECL voltage levels known as PECL. Various ECL and PECL differential receivers have been designed. See for example U.S. Pat. No. 5,479,115, which uses BiCMOS, and U.S. Pat. No. 5,570,042, using CMOS. An example of a bipolar ECL receiver is found in U.S. Pat. No. 5,448,183.
While such ECL and PECL differential receivers are effective, using a standard CMOS process is highly desirable, as circuits become more integrated as pricing pressures intensify. Another desirable feature is a wide common-mode input range so that the input voltage does not have to fall in a strict narrow voltage range. Common-mode variations affect both of the differential signals by the same amount so that data is not lost. Termination, power-supply variations, and voltage drops across transmission lines can alter common-mode input voltages. Using differential input signals cancels out these variations since both inputs are altered by the same amount. However, as the change in input voltages increases, some receivers are less responsive and may even fail. Thus, receivers often have a limited common-mode range. See U.S. Pat. No. 4,958,133 for a receiver with a wide common-mode range. Unfortunately, that receiver uses a bi-stable amplifier, which can be temperamental.
Self-Biased CMOS Differential Receiver
Another CMOS differential receiver is disclosed by Chappell et al. in "Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity", IEEE JSSCC, vol. 23, no. 1, pp. 59-67 (February 1988). The standard CMOS current-mirrored differential amplifier is compared to several variations, including a self-biased receiver. FIG. 1 is a diagram of a prior-art self-biased CMOS differential receiver. P-channel transistors 22, 24 have their gates connected together and to the drain of p-channel transistor 22 so that they have the same gate-to-source voltage and thus the same approximate current drive. This is known as a current mirror. N-channel transistors 26, 28 are a differential pair receiving an input voltage Vin and a reference voltage Vref on their gates. As Vin rises above Vref, n-channel transistor 26 has a higher current drive than n-channel transistor 28, causing the drain of n-channel transistor 26 to fall in voltage while the drain of n-channel transistor 28 rises in voltage. The change in voltage is amplified further by inverter 21 and output.
Tail n-channel transistor 29 has its gate controlled by a reference voltage in standard CMOS sense amplifiers. For self-biasing, the gate of tail n-channel transistor 29 is instead connected to node 30, which is connected to the gates of the current-mirror p-channel transistors 22, 24. Thus, a separate bias voltage for tail n-channel transistor 29 is not required.